Lecture 3a: The Logic Toolkit:

- Many ways to implement a logic function. Designer must choose which one is best based on design constraints.

- Many basic logic gates that are used to great effect in VLSI design.

- CMOS NAND, NOR, INVERT.

o Simple structures, easy to use and implement.

o Good for small number of inputs, single gate implementations of large logic functions get big.

o Mostly a problem with PMOS tree growing too quickly.

o Can combined smaller gates in a circuit to implement larger functions.

§ Trade off of speed of number of gates to size of implementing function in one gate.

- Examples of more complex logic gates that can be implemented using NAND, NOR and Invert.

o N:1 Multiplexor.

§ N inputs, one output. Select lines used to select which input is passed to the output. Usually non-inverting.

· Best implemented with a NAND-NAND logic tree structure.

- XOR/XNOR.

o Truth tables for XOR. Detects odd number of bits.

o 3 input XOR works like a 2, 2-input XOR’s cascaded together.

§ Implemented as A^B + AB^ (INVERT, NAND, NAND).

§ Can implement using a 2:1 MUX.

- Passive CMOS logic gates.

o The pass gate (also Transmission gate or “T”-gate).

§ Parallel connection of NMOS and PMOS.

§ Gate of NMOS connected to signal, PMOS connected to signal^.

§ NMOS passes a good ‘0’, PMOS passes a good ‘1’.

· Depending on Vt and Vdd, some people use an NMOS only pass gate and live with Vt drop.

o If pass gate “off”, output is said to be “high impedance” or “floating”.

§ MORE ON FLOATING OUTPUTS IN THE NEXT LECTURE.

o No direct path to power or ground. Must pass through another CMOS gate to get to a rail. “Passive” gate, not actively pulling output to a rail.

o Pass gates regularly used to build N:1 Mux.

o Driving characteristics are not good. Looks like a resistor in series with driving gate.

§ DO NOT CASCADE MANY OF THESE IN SERIES WITHOUT A CMOS GATE TO “REPEAT” THE SIGNAL.

· Signal strength with degrade quickly due to series R connections.

§ Sizing pass gates difficult.

· PMOS gate only there to help pull up the output beyond VDD-Vtn.

o NMOS gate gets very resistive when output gets close to Vdd-Vt.

o Since PMOS is not doing too much work (NMOS is helping), size Wp = Wn.

· To size Wn, just assume the NMOS is another series connected NMOS in the driving gate and size appropriately.

- The tri-state inverter.

o Looks like an inverter in series with a pass gate with the N and P of the pass gate not connected on one side.

o Three states, output = high, low and high-impedance.

o Always place clock in the middle to avoid noise problems (more on this in lecture 4b and 5a).

o Useful in implementing MUXes and tri-state busses.

§ A tri-state bus is a set of signals that have multiple drivers.

· Need a bus “arbiter” that selects which driver is active.

· Non-active drivers must have high-impedance outputs or signal conflict occurs.

· Not used too much anymore since arbitration takes time, must ensure drivers are mutually exclusive and the bus gets loaded by multiple drivers.

· Better processes, more layers of metal, less need to “share” busses.

- Complex CMOS gates.

o Can combine series and parallel connections of transistors to get a complex logic function in one gate.

o NMOS tree implements f^, PMOS implements f.

o A series connection in the NMOS tree infers a parallel connection in PMOS.

o CMOS an INVERTING logic family.

o Very easy to implement functions of the form f = (logic equation)^.

§ In this case, AND terms are series NMOS connections, OR terms or parallel NMOS connections.

§ Build NMOS tree, then build complementary PMOS tree using NMOS structure as a guide.

o Make sure that you have reduced logic equation to minimum “sum of products” form.

o Use K-maps if needed.

§ Can try to group the zeros in the K-map to get the function in the form f = (equation)^.

o If equation is not in the f = (equation)^, try to use DeMorgan’s law to build it.

o If have true and compliment of inputs available, use the complements of the inputs to implement f.

o If not, you can implement f^ and invert the output.

§ Two gate implementation but usually ok.

o Do not want too many transistors (esp ‘P’ in series or tree gets too big).

§ Look for paths in NMOS and PMOS tree that are not possible and eliminate them.

· CMOS XOR (assume signal and compliments are available).

o Notice that PMOS tree has two connections that are never possible. Remove them (they just add load).

- Pseudo-NMOS gates.

o Called pseudo-NMOS since NMOS only logic families used a long time ago (this family uses one PMOS transistor).

o NMOS tree is same as CMOS gate.

o PMOS tree replaced with one PMOS with gate tied to Vss.

o If NMOS tree is not pulling down, PMOS transistor is pulling up.

o Size NMOS tree as would a CMOS gate.

o PMOS size is more difficult.

§ If PMOS Drive strength is equal to NMOS drive strength, Vol will only be Vdd/2.

§ Must make PMOS “weak” in relation to NMOS such that Vol of gate is below Vtn (or will have problems in next gate).

o VTC curve depends on size of PMOS.

§ Pulldown starts just after Vtn.

§ Slope depends on Wp.

§ Vol depends on Wp.

o Also called “ratioed” gates since the ratio of Wp to Wn effective determines the output characteristics.

o Good:

§ This is a smaller logic family than CMOS since it does not have to have the complimentary PMOS tree.

§ Less load seen by driving gate.

§ Can implement wide NOR structures easily.

o Bad:

§ Very bad output characteristics since it is not a “rail to rail” logic family.

§ Noise problems.

§ Output voltages shift with process corner.

§ Rise times are very bad (weak P).

· Non-symmetric rise and fall times.

- CVSL

o Cascade Voltage Switch Logic.

o Build both f and f^ in two NMOS trees.

o All signals and their compliments needed.

o Generates both f and f^ simultaneously.

§ Called “dual-rail” logic family.

o Pull-up tree is a “cross-coupled” pair of PMOS transistors.

§ One side pulls down, that low output is input to other tree’s PMOS, Other output is pulled up.

§ The pulled-up output shuts off the other PMOS transistor.

o Good:

§ Outputs are either Vdd or Vss.

§ Generate complex logic functions without comp PMOS tree.

§ Like pseudo-NMOS, less input cap.

§ Generate both true and comp simultaneously. Good for XOR like functions.

o Bad:

§ Not very good noise immunity.

§ A lot of overhead for simple functions.

§ Have P-N “fight” until other side “flips” output.

· Need to make PMOS weak in order to “win” fight.

· SLOWER THAN NORMAL CMOS because of this.

§ Non-symmetric rise and fall times. Bad pull-up.

Lab Tutorial: How to use Verilogger.

RTL and concurrent programming languages.

- Register Transfer Level programming.

o Models the memory elements (registers) of a digital circuit and describes the boolean equations between the registers.

§ One “stage” or registers usually referred to as a “pipeline stage”.

o Higher level of abstraction used to design the logic of a machine.

o Use RTL to define a machines operation and include the concept of timing.

o It is a “structural” specification expressing the behavior of a digital system as a hierarchical interconnection of sub-modules.

o Usually, the architects will build the RTL model.

§ This model includes all signals in a design.

§ Is usually partitioned as the hardware would be.

· That is, one module for an adder, one for a memory, etc.

§ Describes what is happening (logically) in the machine in each clock cycle.

o VERY useful in finding logic bugs in a design.

o RTL easier to design than circuits.

o First build RTL and verify that it solves problem design addresses.

o Use RTL as a “roadmap” to design circuits

§ Human interface builds “custom” circuits.

§ Synthesis software tools “compile” RTL into circuit.

· MORE ON THIS IN LECTURE 7a and 7b.

o RTL programming most useful in complex designs where logic equations are difficult to derive.

o Allows partitioning of problem into “logic” design and “circuit” design. Both are a part of VLSI design.

- Above RTL programming is “behavioral” programming.

o Only describes logic functions.

o No real concept of timing.

o Can be done in C code or any other high level language.

o Uses “traditional” programming constructs like ‘if’ statements.

- Below RTL programming is “gate level” programming.

o Program only consists of instances of hardware gates.

o Usually can netlist a schematic to a gate-level program to verify that circuit logically implements the correct function.

o Can even go to the transistor level, but the transistors are only modeled as digital switches.

- Concurrent Programming languages.

o HDL is a “hardware description language” that allows the programmer to describe a digital circuit in a way that is close to the operation of the circuit.

o Concurrent programming allows the designer to write several blocks of code (or threads) to be executed simultaneously.

o This models the way an actual circuit operates. That is, hardware is always operating.

§ Any time a signal transitions, the gate will calculate the new output value.

§ Circuits are inherently parallel operators.

o HDL’s are usually “event driven” languages.

§ A signal transition is an event.

§ At each event, the HDL checks to see what code is “triggered” by the event.

§ The HDL then “schedules” new transitions to occur in the future based on the code blocks that were triggered by the event.

§ HDL theory is complex and needs another course to fully describe it.

- Verilog

o See the pointer on the web page to get a better description on verilog. Called “Bucknell Handbook on Verilog HDL”.

o Covers all the most useful syntax.

o Verilog is the HDL we use in en160.

o Very widely used in industry.

o Not enough time in class to teach all subtleties of language.

§ This is “primer”.

· Need to read pointer on web page and use the verilog book to learn language to do homeworks.

o Pretty easy syntax.

o Can be written like a circuit or like a high level program.

o Basics of Verilog.

§ Programs are made up of “modules”.

§ Each module defines the input and output signals associated with it.

§ Input and output signals are nets.

· Can make “vectored” signals that make a bus.

· By default, all nets and registers are single bits.

· Use the X’v# format (X is width, v is “base format” binary, dec, hex, etc, # is the value) when assigning values.

§ Registers are memory elements.

· Registers store the last value that was “proceduraly” assigned to them (just like variables in C code).

· Procedural assignments can only occur in initial and always blocks.

· Can assign values to REGISTERS ONLY in initial/always blocks.

· Need to use ASSIGN keyword to assign a value to a wire.

o Wires must be continuously driven.

o CAREFUL WITH THE USE OF NETS AND REGISTERS, VERY EASY TO MAKE MISTAKES HERE.

§ Sequential logic constructs.

· Initial: begins operation at time 0.

· Always: starts at time zero and loops forever.

· Use begin - end instead of {}.

· Use blocking and non-blocking delays to prevent a piece of code from executing for a defined number of VTU’s (verilog time units).

· Sequential logic = registers.

· Assign statements = combinational logic gates.